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| 包裝類型 | 數量 | 單價: | 總計 |
|---|---|---|---|
| 條帶式包裝 | 1 | NT$55.160 | NT$55.16 |
| 總計 價格 | NT$55.16 | ||
| 數量 | 價格 |
|---|---|
| 1+ | NT$55.160 |
| 10+ | NT$37.100 |
| 50+ | NT$34.930 |
| 100+ | NT$32.760 |
| 250+ | NT$30.830 |
| 500+ | NT$30.400 |
| 1000+ | NT$27.320 |
| 2500+ | NT$26.800 |
產品訊息
產品總覽
The SN74LVCH16373ADGGR is a 16-bit transparent D-Type Latch with 3-state outputs. It is designed for 1.65 to 3.6V VCC operation. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers and working registers. It can be used as two 8-bit latches or one 16-bit latch. When the LE input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs. A buffered OE\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pull-up components. OE\ does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
- Ioff Supports live insertion, partial-power-down mode and back-drive protection
- Supports mixed-mode signal operation
- Bus hold on data inputs eliminates the need for external pull-up or pull-down resistors
- Latch-up performance exceeds 250mA per JESD 17
- Green product and no Sb/Br
應用
Communications & Networking, Medical, Power Management
技術規格
74LVC373
Tri State
24mA
TSSOP
1.65V
16bit
7416373
85°C
-
No SVHC (27-Jun-2018)
Transparent
4.2ns
TSSOP
48Pins
3.6V
74LVC
-40°C
-
MSL 1 - Unlimited
法規與環境保護
承擔產品生產最後程序之國家原產地:Malaysia
承擔產品生產最後程序之國家
RoHS
RoHS
產品合規憑證

