TLC555IDR

The TLC555IDR is a monolithic Low Power Timer fabricated using the TI LinCMOS™ process. Because of its high input impedance, this device uses smaller timing capacitors than those used by the NE555. As a result, more accurate time delays and oscillations are possible. Power consumption is low across the full range of power supply voltage. It has a trigger level equal to approximately 1/3rd of the supply voltage and a threshold level equal to approximately 2/3rd of the supply voltage. This level can be altered by use of the control voltage terminal (CONT). When the trigger input (TRIG) falls below the trigger level, the flip-flop is set and the output goes high. If TRIG is above the trigger level and the threshold input (THRES) is above the threshold level, the flip-flop is reset and the output is low. The reset input (RESET) can override all other inputs and can be used to initiate a new timing cycle. If RESET is low the flip-flop is reset and the output is low.

• Capable of operation in astable mode
• CMOS output capable of swinging rail to rail
• Output fully compatible with CMOS, TTL and MOS
• Low supply current reduces spikes during output transitions
• ESD protection exceeds 2000V per MIL-STD-883C, method 3015.2
• Green product and no Sb/Br

應用

Clock & Timing, Communications & Networking