AD9510BCPZ

AD9510 is a multi-output clock distribution IC along with an on-chip phase-locked loop (PLL) core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this device. The PLL section consists of a programmable reference divider (R); a low noise, phase frequency detector (PFD); a precision charge pump (CP); and a programmable feedback divider (N). By connecting an external voltage-controlled crystal oscillator (VCXO) or voltage-controlled oscillator (VCO) to the CLK2 and CLK2B pins, frequencies of up to 1.6GHz can be synchronized to the input reference. Application includes low jitter, low phase noise clock distribution clocking high-speed ADCs, DACs, DDSs, DDCs, DUCs, and mixed-signal front ends (MxFEs), high-performance wireless transceivers, high-performance instrumentation, broadband infrastructure.

• Low phase noise, phase-locked loop core
• Programmable dual modulus prescaler
• Programmable charge pump (CP) current
• Phase select for output-to-output coarse delay adjust
• Serial control port
• Input frequency range from 0 to 250MHz (VS=3.3V ± 5%, VS ≤ VCPS ≤ 5.5V, TA=25°C)
• Typical input sensitivity is 150mV p-p (VS=3.3V ± 5%, VS ≤ VCPS ≤ 5.5V, TA=25°C)
• Operating temperature rating range from -40 to +85°C
• 64-lead frame chip scale package [LFCSP-VQ]

附註

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