AD9544BCPZ

AD9544 is a 10-output, dual DPLL, 1pps synchronizer and jitter cleaner. The 10-clock output of the synchronized to any one of up to four input references. The digital phase-locked loops (DPLLs) reduce the timing jitter associated with the external references. The digitally controlled loop and holdover circuitry continuously generate a low jitter output signal, even when all reference inputs fail. Application includes SyncE and GPS synchronization and jitter clean-up, optical transport networks (OTN), SDH, and macro and small cell base stations, OTN mapping/demapping with jitter cleaning, small base station clocking, including baseband and radio stratum 2, Stratum 3e, and Stratum 3 holdover, jitter clean-up, and phase transient control JESD204B support for analog-to-digital converter (ADC) and digital-to-analog converter (DAC) clocking, cable infrastructures and carrier Ethernet.

• Complies with ITU-T G.8262 and Telcordia GR-253
• Supports telcordia GR-1244, ITU-T G.812, G.813, G.823, G.824, and G.825
• 2 differential or 4 single-ended input references
• Crosspoint mux interconnects reference inputs to PLLs
• Supports embedded (modulated) input/output clock signals
• Fast DPLL locking modes
• External EEPROM support for autonomous initialization
• VDDIOA, VDDIOB range from 1.71 to 3.465V (VDD = 1.8V and TA = 25°C)
• Typical configuration is 560mW (typical values apply for VDD = 1.8V)
• 48-lead LFCSP package, temperature range from -40°C to +85°C

附註

ADI products are only authorized (and sold) for use by the customer and are not to be resold or otherwise passed on to any third party