S25FL127SABMFI101

S25FL127SABMFI101 is a 3.0V SPI flash memory. It features MirrorBit technology that stores two data bits in each memory array transistor. The Eclipse architecture dramatically improves the program and erases performance. It has 65nm process lithography. This device connects to a host system via an SPI. Traditional SPI single-bit serial input and output (Single I/O or SIO) is supported as well as optional two-bit (dual I/O or DIO) and four-bit (quad I/O or QIO) serial commands. This multiple-width interface is called SPI multi-I/O or MIO. The eclipse architecture features a page programming buffer that allows up to 128 words (256 bytes) or 256 words (512 bytes) to be programmed in one operation, resulting in faster effective programming and erase than prior generation SPI program or erase algorithms.

• 128Mb density, 0.065µm MirrorBit process technology
• 108MHz speed, 2.7V to 3.6V supply voltage
• 6Mbps (50MHz) normal read speed (SDR), 13.5Mbps (108MHz) fast read speed (SDR)
• 27Mbps (108MHz) dual read speed (SDR), 54Mbps (108MHz) quad read speed (SDR)
• 100,000 minimum program-erase cycles per sector
• 20 year minimum data retention
• Advanced sector protection, auto boot mode, erase suspend/resume
• Program suspend/resume, ±2µA max input leakage current at (VCC = VCC max)
• 63mA power on reset current at (RESET#, CS# = VCC; SI, SCK = VCC or VSS)
• Industrial temperature range from -40°C to +85°C, 8-pin SOIC package