PCIE-ROOTPORT-AD

PCIE-ROOTPORT-AD is a PCIe root port adapter. Microchip PolarFire® FPGAs support fully integrated PCIe Endpoint and Root Port subsystems with optimized embedded controller blocks that use the physical layer interface (PHY) of the transceiver. Each PolarFire device includes two embedded PCIe subsystem (PCIESS) blocks that can be configured either separately, or as a pair, using the PF_PCIE IP configurator in the Libero® System-on-Chip (SoC) PolarFire software. The PF_PCIE IP core is compliant with the PCI Express Base Specification, Revision 2.1. It implements memory-mapped advanced microcontroller bus architecture (AMBA) advanced extensible interface 4 (AXI4) access to PCIe space, and PCIe access to the memory-mapped AXI4 space. PCIe interface is used across many applications, including the following: automotive applications, datacentre infrastructure, enterprise infrastructure and defence systems.

• PolarFire transceivers for 2.5 and 5.0Gbps line speeds
• Native x1, x2, and x4 lane-support PCIe block (down-configurable/downgradable)
• Root port support for up to two 32bit or one 64bit BAR
• PCI express base specification 1.1- and 2.1-compliant
• Legacy PCI power management support
• 64-bit AXI host and server interface to the FPGA fabric
• End-to-end data integrity

Contents

PCIe root port adapter card, 12V, 5A AC power adapter and cord, Quickstart card.