CY2304SXI-1

CY2304SXI-1 is a CY2304 zero delay buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom, and other high performance applications. The part has an on-chip phase-locked loop (PLL) that locks to an input clock presented on the REF pin. The PLL feedback is required to be driven into the FBK pin, and can be obtained from one of the outputs. It can accept the same input clock and distribute it in a system. In this case, the skew between the outputs of two devices is guaranteed to be less than 500ps. The PLL enters a power down state when there are no rising edges on the REF input. In this mode, all outputs are three-stated and the PLL is turned off, resulting in less than 25μA of current draw.

• Zero input-output propagation delay, adjustable by capacitive load on FBK input
• Multiple configurations
• Multiple low-skew outputs
• Supply voltage range from 3 to 3.6V
• 8-pin SOIC (150 Mils) package
• Industrial temperature range
• Operating ambient temperature range from 0 to 70°C