CY2305SXC-1.

CY2305SXC-1 is a low-cost 3.3V zero delay buffer designed to distribute high-speed clocks. It accepts one reference input and drives out five low-skew clocks. It has on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. It can accept the same input clock and distribute it. In this case, the skew between the outputs of two devices is guaranteed to be less than 700ps. The CY2305 PLL enters a power-down mode when there are no rising edges on the REF input. In this state, the outputs are three-stated and the PLL is turned off, resulting in less than 25.0μA current draw for this part.

• Zero input-output propagation delay
• 60ps typical cycle-to-cycle jitter (high drive)
• One input drives five outputs
• 85ps typical output-to-output skew
• Compatible with Pentium-based systems
• 3.3V operation
• 8-pin SOIC package
• Commercial Operating temperature (ambient) range from 0 to 70°C