MT48LC8M16A2P-6A IT:L

MT48LC8M16A2P-6A IT:L is a 128Mb SDRAM and a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x16’s 33,554,432-bit banks are organized as 4096 rows by 512 columns by 16 bits.

• Operating supply voltage range is 3V to 3.6V
• 8Meg x 16 (2 Meg x 16 x 4 banks) configuration, LVTTL-compatible inputs and outputs
• Packaging style is 54-pin TSOP II (400 mil)
• Timing (cycle time) is 6.0ns at CL = 3 (x16 only)
• Industrial temperature range is –40˚C to +85˚C
• Clock frequency is 167MHz, auto refresh is 64ms, 4096-cycle refresh
• Fully synchronous to all signals registered on positive edge of system clock
• Internal, pipelined operation to column address can be changed every clock cycle
• Internal banks for hiding row access/precharge
• Auto precharge, includes concurrent auto precharge and auto refresh modes