74HC74D-Q100,118

74HC74D-Q100,118 is a dual positive-edge triggered D-type flip-flop with individual data (nD), clock (nCP), set (n active-low SD) and reset (n active-low RD) inputs, and complementary nQ and n active-low Q outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition, will be stored in the flip-flop and appear at the nQ output. The Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This enables the use of current-limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (grade 1) and is suitable for use in automotive applications.

• Symmetrical output impedance, low power dissipation
• High noise immunity, balanced propagation delays
• Specified in compliance with JEDEC standard no. 7A
• CMOS input levels
• Input transition rise and fall rate is 625ns/V max at VCC = 2.0V
• Input leakage current is ±1.0μA max at VI = VCC or GND; VCC = 6.0V
• Total power dissipation is 500mW maximum at Tamb = -40°C to +125°C
• Propagation delay is 265ns max at -40°C to +125°C, VCC = 2.0V
• SO14 package
• Temperature range from -40°C to +125°C