產品訊息
產品總覽
The 74LVC1G07GW,125 is a non-inverting Buffer with open-drain output. The open drain output can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. Inputs can be driven from either 3.3/5V devices. This feature allows the use of this device in a mixed 3.3 and 5V environment. Schmitt-trigger action at all inputs makes the circuit tolerant for slower input rise and fall time. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
- High noise immunity
- CMOS low power consumption
- Direct interface with TTL levels
- Complies with JEDEC standard
- 5V Tolerant input/output for interfacing with 5V logic
- Latch-up performance exceeds 250mA
- Inputs accept voltages up to 5V
應用
Industrial, Automation & Process Control, Signal Processing, Automotive
警告
Market demand for this product has caused an extension in leadtimes. Delivery dates may fluctuate. Product exempt from discounts.
技術規格
Buffer, Non Inverting
TSSOP
5Pins
5.5V
741G07
125°C
-
No SVHC (25-Jun-2025)
74LVC1G07
TSSOP
1.65V
74LVC
-40°C
-
MSL 1 - Unlimited
74LVC1G07GW,125 的替代選擇
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法規與環境保護
承擔產品生產最後程序之國家原產地:Malaysia
承擔產品生產最後程序之國家
RoHS
RoHS
產品合規憑證