74LVC2G04GV,125

74LVC2G04GV,125 is a dual inverter. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as translator in mixed 3.3V and 5V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. It features ESD protection (HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000V, CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000V). It complies with JEDEC standard (JESD8-7 (1.65V to 1.95V), JESD8-5 (2.3V to 2.7V), JESD8C (2.7V to 3.6V), JESD36 (4.6V to 5.5V).

• Wide supply voltage range from 1.65V to 5.5V
• Overvoltage tolerant inputs to 5.5V, high noise immunity
• CMOS low power dissipation, direct interface with TTL levels
• IOFF circuitry provides partial power-down mode operation
• Input leakage current is ±0.1μA typical at (VI=5.5V or GND;VCC = 0V to 5.5V, -40°C to +85°C)
• Supply current is 0.1μA typical at (VI=5.5V or GND; IO = 0A;VCC = 1.65V to 5.5V, -40°C to +85°C)
• Input capacitance is 2.5pF typical at (-40°C to +85°C)
• Propagation delay is 3.5ns typical at (VCC = 1.65V to 1.95V, -40°C to +85°C)
• Operating temperature range from -40°C to +125°C
• TSOP6 package

警告

Market demand for this product has caused an extension in leadtimes. Delivery dates may fluctuate. Product exempt from discounts.