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MPC8358EVVAGDGA
Microprocessor, PowerQUICC II Pro Series, 400 MHz, 32bit, 64KB, 1.14 V to 1.26 V, TBGA-740
產品總覽
The PowerQUICC II Pro series PowerQUICC II Pro Processor with DDR2, TDM and PCI interface. A major component of this device is the e300 core, which includes 32kB of instruction and data cache and is fully compatible with the Power Architecture™ 603e instruction set. The new QUICC engine module provides termination, interworking and switching between a wide range of protocols including ATM, Ethernet, HDLC and POS. The QUICC Engine module's enhanced interworking eases the transition and reduces investment costs from ATM to IP based systems. The other major features include a dual DDR SDRAM memory controller for the MPC8360E, which allows equipment providers to partition system parameters and data in an extremely efficient way, such as using one 32-bit DDR memory controller for control plane processing and the other for data plane processing. The MPC8358E has a single DDR SDRAM memory controller.
- e300 PowerPC processor core (enhanced version of the MPC603e core)
- Serial DMA channel for receive and transmit on all serial channels
- QUICC engine module peripheral request interface (for SEC, PCI, IEEE standard 1588™)
- 10/100Mbps Ethernet/IEEE standard 802.3™ CDMA/CS interface through a media-independent interface
- Ethernet over first mile IEEE 802.3ah
- Extensive support for ATM statistics and Ethernet RMON/MIB statistics
- HDLC up to 70Mbps full-duplex and HDLC BUS up to 10Mbps
- Two UTOPIA/POS interfaces on the MPC8360E supporting 124 MultiPHY each
- Two serial peripheral interfaces (SPI), SPI2 is dedicated to Ethernet PHY management
- Security engine
- Single DDR SDRAM memory controller - Read-modify-write support and supports auto refreshing
- Local bus controller (LBC) - Multiplexed 32-bit address and data operating at up to 133MHz
- Programmable interrupt controller (PIC) - Unique vector number for each interrupt source
- DMA controller - Four independent virtual channels and misaligned transfer capability
- DUART - Two 4-wire interfaces (RxD, TxD, RTS, CTS)
- System timers - Periodic interrupt timer, real-time clock and software watchdog timer
- Eight general-purpose timers
- IEEE Std. 1149.1™-compliant, JTAG boundary scan
- Integrated PCI bus and SDRAM clock generation
應用
Communications & Networking
產品訊息
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