FPGA, Cyclone III, PLL, 128 I/O's, 402 MHz, 1.15 V to 1.25 V, QFP-240
- 4 Phase-locked loops
- 227 Differential channels
- Hot-socketing operation support
- Routing architecture optimized for design separation flow with the Quartus® II software
- Ability to disable external JTAG port
- Error detection (ED) cycle indicator to core
- Internal oscillator enables system monitor and health check capabilities
- High memory-to-logic and multiplier-to-logic ratio
- High I/O count, low-and mid-range density devices for user I/O constrained applications
- Remote system upgrade without the aid of an external controller
- Dedicated cyclical redundancy code checker circuitry to detect single-event upset (SEU) issues
Automotive, Consumer Electronics, Wireless, Aerospace, Defence, Military, Industrial, Imaging, Video & Vision
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