AD9518-4ABCPZ

AD9518-4 provides a multi-output clock distribution IC function with sub picosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 1.45GHz to 1.80GHz. Optionally, an external VCO/VCXO of up to 2.4GHz can be used. It emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applications with demanding phase noise and jitter requirements. It features six LVPECL outputs (in three pairs). The LVPECL outputs operate to 1.6GHz. Each pair of outputs has dividers that allow both the divide ratio and coarse delay (or phase) to be set. The range of division for the LVPECL outputs is 1 to 32. Application includes low jitter, low phase noise clock distribution, 10/40/100 Gb/sec networking line cards, including SONET, synchronous Ethernet, OTU2/3/4, forward error correction (G.710), clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs, high performance wireless transceivers, ATE and high performance instrumentation.

• Low phase noise, phase-locked loop (PLL), reference monitoring capability
• Automatic revertive and manual reference switchover/holdover modes
• Programmable delays in path to PFD, digital or analogue lock detect, selectable
• Each output pair shares two cascaded 1-to-32 dividers with coarse phase delay
• Automatic synchronization of all outputs on power-up
• VS range from 3.135 to 3.465V (VS=VS-DRV= 3.3V ± 5%, VS ≤ VCP ≤ 5.25V, TA=25°C, typ)
• Frequency range from 1450 to 1800MHz (VS=VS-LVPECL=3.3V ± 5%, VS ≤ VCP ≤ 5.25V, TA=25°C, typ)
• Typical frequency pushing is 1MHz/V (VS=VS-LVPECL=3.3V ± 5%, VS ≤ VCP ≤ 5.25V, TA=25°C, typ)
• Typical ICP sink/source high value is 4.8mA (CPRSET=5.1Kohm, VS ≤ VCP ≤ 5.25V, TA=25°C, typ)
• 48-lead LFCSP package, temperature range from -40°C to +85°C

附註

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