AD9522-3BCPZ

AD9522-3 provides a multioutput clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. It is a serial interface that supports both SPI and I²C® ports. An in-package EEPROM can be programmed through the serial interface and store user-defined register settings for power-up and chip reset. It features 12 LVDS outputs in four groups. Any of the 800MHz LVDS outputs can be reconfigured as two 250MHz CMOS outputs. Application includes low jitter, low phase noise clock distribution, clock generation and translation for SONET, 10Ge, 10GFC, synchronous Ethernet, OTU2/3/4, forward error correction (G.710), clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs, high performance wireless transceivers ATE and high-performance instrumentation, broadband infrastructures.

• Low phase noise, phase-locked loop (PLL), reference monitoring capability
• Revertive automatic and manual reference switchover/holdover modes
• Glitch-free switchover between references, automatic recovery from holdover
• Digital or analogue lock detect, selectable, automatic synchronization of all outputs on power-up
• SPI- and I²C-compatible serial control port, non-volatile EEPROM stores configuration settings
• VS is 3.3V (typ, 3.3V ± 5%, VS ≤ VCP ≤ 5.25V, TA = 25°C)
• Frequency range from 1720 to 2250MHz (VS = 3.3V ± 5%, VS ≤ VCP ≤ 5.25V, TA = 25°C)
• Phase noise at 1KHz offset is -62dBc/Hz (typ, LVDS output, fVCO = 1985MHz, fOUT = 662MHz)
• Pulse width high/low is 1.8ns (min, VS = 3.3V ± 5%, VS ≤ VCP ≤ 5.25V, TA = 25°C)
• 64-lead LFCSP-VQ package, temperature range from -40°C to +85°C

附註

ADI products are only authorized (and sold) for use by the customer and are not to be resold or otherwise passed on to any third party