ADF4382ABCCZ

ADF4382ABCCZ is a high-performance, ultralow jitter, fractional-N phased-locked loop (PLL) with an integrated voltage-controlled oscillator (VCO) ideally suited for the local oscillator (LO) generation for 5G applications or data converter clock applications. The high-performance PLL has a figure of merit of -239dBc/Hz, low 1/f noise, and high PFD frequency of 625MHz in integer mode that can achieve ultralow in-band noise and integrated jitter. The ADF4382A can generate frequencies in a fundamental octave range of 11.5GHz to 21GHz, thereby eliminating the need for subharmonic filters. For multiple data converter clock applications, the ADF4382A automatically aligns its output to the input reference edge by including the output divider in the PLL feedback loop. Applications include high performance data converter clocking, wireless infrastructure (MC-GSM, 5G, 6G), test and measurement.

• Fundamental output frequency range from 11.5GHz to 21GHz
• Divide by 2 output frequency range from 5.75GHz to 10.5GHz
• Divide by 4 output frequency range from 2.875GHz to 5.25GHz
• Multichip output phase alignment, 3.3V and 5V power supplies
• ADIsimPLL™ loop filter design tool support, integrated RMS jitter at 20 GHz = 31fs (ADC SNR method)
• Integrated RMS jitter at 20GHz = 20fs (integration bandwidth:100Hz to 100MHz)
• Phase noise floor is -156dBc/Hz typical at (3.3V supply group 1 pins voltage (V3.3V-1) = 3.3V)
• Spurious fPFD is -90dBc typical at (3.3V supply group 1 pins voltage (V3.3V-1) = 3.3V)
• Propagation delay temperature coefficient is 0.06ps/°C typical at (REF-SEL = 0)
• Operating temperature range from -40°C to +105°C, 48-terminal LGA package

附註

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