HMC7044LP10BETR

HMC7044 is a high performance, dual-loop, integer-N jitter attenuator capable of performing reference selection and generation of ultralow phase noise frequencies for high speed data converters with either parallel or serial (JESD204B type) interfaces. It features two integer mode PLLs and overlapping on-chip VCOs that are SPI-selectable with wide tuning ranges around 2.5GHz and 3GHz, respectively. This device is designed to meet the requirements of GSM and LTE base station designs and offers a wide range of clock management and distribution features to simplify baseband and radio card clock tree designs. It provides 14 low noise and configurable outputs to offer flexibility in interfacing with many different components including data converters, field-programmable gate arrays (FPGAs), and mixer local oscillators (LOs). It is used in application such as data converter clocking, microwave baseband cards, phase array reference distribution etc.

• Ultralow rms jitter is 44fs typical at (12KHz to 20MHz, at 2457.6MHz)
• Upto 14 LVDS, LVPECL, or CML type device clocks (DCLKs) from PLL2
• SPI-programmable phase noise vs. power consumption, on-board regulators for excellent PSRR
• SYSREF valid interrupt to simplify JESD204B synchronization, narrow-band, dual core VCOs
• Upto 2 buffered voltage controlled oscillator (VCXO) outputs
• Upto 4 input clocks in LVDS, LVPECL, CMOS, and CML modes
• Frequency holdover mode to maintain output frequency
• Frequency holdover mode to maintain output frequency
• Loss of signal (LOS) detection and hitless reference switching
• Operating temperature is -40°C to +85°C, package style is 68-lead LFCSP-VQ

附註

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