IS42S32800J-6BLI

IS42S32800J-6BLI is a 256Mb synchronous DRAM that achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 256Mb SDRAM is organized in 2Meg x 32bit x 4 banks. It is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V Vdd and 3.3V Vddq memory systems containing 268,435,456 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 67,108,864-bit bank is organized as 4,096 rows by 512 columns by 32 bits. The 256Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL compatible.

• Fully synchronous; all signals referenced to a positive clock edge
• Internal bank for hiding row access/precharge, single power supply is 3.3V ± 0.3V
• LVTTL interface, programmable burst sequence: sequential/interleave
• Auto refresh (CBR), self refresh, random column address every clock cycle
• Programmable active-low CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write operations capability
• Burst termination by burst stop and precharge command
• 166MHz frequency, 6ns speed
• 90-Ball TF-BGA package
• Industrial rating range from -40°C to +85°C