IS43DR16640B-25DBLI

The IS43DR16640B-25DBLI is a 1Gb DDR2 SDRAM with 400MHz frequency, DDR2-800D speed grade and 64Mb x 16 organization. For application flexibility, burst length, burst type, CAS# latency, DLL reset function, write recovery time (WR) are user defined variables and must be programmed with a Mode Register Set (MRS) command. Additionally, DLL disable function, driver impedance, additive CAS latency, ODT (On Die Termination), single-ended strobe and OCD (off chip driver impedance adjustment) are also user defined variables and must be programmed with an Extended Mode Register Set (EMRS) command. Contents of the Mode Register (MR) or Extended Mode Registers EMR[1] and EMR[2] can be altered by re-executing the MRS or EMRS Commands. Even if the user chooses to modify only a subset of the MR, EMR[1] or EMR[2] variables, all variables within the addressed register must be redefined when the MRS or EMRS commands are issued.

• 8 Internal banks for concurrent operation
• 4-bit Prefetch architecture
• Programmable CAS latency - 3, 4, 5, 6 and 7
• Programmable additive latency - 0, 1, 2, 3, 4, 5 and 6
• Write latency = Read Latency-1
• Sequential or interleave programmable burst sequence
• 4 and 8 programmable burst length
• Automatic and controlled precharge command
• Power down mode
• Auto refresh and self refresh
• 7.8µs (8192 cycles/64ms) Refresh interval
• ODT (On-Die Termination)
• Weak strength data-output driver option
• Bidirectional differential data strobe (single-ended data-strobe is an optional feature)
• On-chip DLL aligns DQ and DQs transitions with CK transitions
• DQS# can be disabled for single-ended data strobe
• Read data strobe supported (x8 only)
• Differential clock inputs CK and CK#
• VDD and VDDQ = 1.8V ±0.1V
• PASR (Partial Array Self Refresh)

應用

Industrial, Commercial, Automotive