MT53E1G32D2FW-046 WT:A

MT53E1G32D2FW-046 WT:A is a mobile LPDDR4 SDRAM. The low-power DDR4 SDRAM (LPDDR4) is a high-speed, CMOS dynamic random-access memory device. This 8-bank device is internally configured with ×16 I/O. Each of the ×16 2,147,483,648-bit banks are organized as 131,072 rows by 1024 columns by 16 bits. LPDDR4 uses a double-data-rate (DDR) protocol on the DQ bus to achieve high-speed operation. The DDR interface transfers two data bits to each DQ lane in one clock cycle and is matched to a 16n-prefetch DRAM architecture.

• 16n prefetch DDR architecture, 8 internal banks per channel for concurrent operation
• Single-data-rate CMD/ADR entry, bidirectional/differential data strobe per byte lane
• Programmable READ and WRITE latencies (RL/WL), programmable and on-the-fly burst lengths (BL=16, 32)
• Directed per-bank refresh for concurrent bank operation and ease of command scheduling
• On-chip temperature sensor to control self refresh rate
• Partial-array self refresh (PASR), selectable output drive strength (DS), clock-stop capability
• 4GB (32Gb) total density, 4266Mb/s data rate per pin
• 1.10V VDD2/0.60V or 1.10V VDDQ operating voltage
• 200-ball TFBGA package
• Operating temperature from -30°C to +85°C