74AUP1G17GW,125

74AUP1G17GW,125 is a single buffer with Schmitt-trigger input. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8V to 3.6V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. It features ESD protection (HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000V, CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000V). It complies with JEDEC standards (JESD8-12 (0.8V to 1.3V), JESD8-11 (0.9V to 1.65V) JESD8-7 (1.2V to 1.95V), JESD8-5 (1.8V to 2.7V), JESD8C (2.7V to 3.6V).

• CMOS low power dissipation, high noise immunity
• Overvoltage tolerant inputs to 3.6V, low noise overshoot and undershoot <lt/> 10% of VCC
• IOFF circuitry provides partial power-down mode operation
• Latch-up performance exceeds 100mA per JESD 78 Class II Level B
• Input leakage current is ±0.75μA maximum at (VI = GND to 3.6V; VCC = 0V to 3.6V)
• Power-off leakage current is ±0.75μA maximum at (VI or VO = 0V to 3.6V; VCC = 0V)
• Supply current is 1.4μA maximum at (VI = GND or VCC; IO = 0A; VCC = 0.8V to 3.6V)
• Propagation delay is 11.1ns maximum at (VCC = 1.1V to 1.3V)
• Operating temperature range from -40°C to +125°C
• TSSOP5 package

警告

Market demand for this product has caused an extension in leadtimes. Delivery dates may fluctuate. Product exempt from discounts.